asynchronous receiver造句
例句與造句
- Uart universal asynchronous receiver transmitter
通用異步接收發(fā)送裝置 - Uart universal asynchronous receiver transmitter
通用異步接收發(fā)送裝置 - Universal asynchronous receiver transmitter
通用同步接收發(fā)送器 - The bluetooth specification supports uart universal asynchronous receiver transmitter and usb transport mechanisms for bluetooth hci packets
Bluetooth規(guī)范支持針對(duì)bluetooth hci數(shù)據(jù)分組的uart （通用異步接收器/傳送器）和usb傳輸機(jī)制。 - In the course of the design , critical technologies are applied , such as digital phase - locked loop , fast fourier transform algorithm , universal asynchronous receiver & transmitter , and so on . in the project , as a important component , the module of monitoring the buses " power quality takes a long time
在設(shè)計(jì)過程中，使用的關(guān)鍵技術(shù)有：使用cpld仿真多路sspc多種狀態(tài)；在對(duì)匯流條電能質(zhì)量的監(jiān)測(cè)過程中采用頻率跟蹤技術(shù)? ?全數(shù)字鎖相環(huán)；應(yīng)用fpga技術(shù)使用fft運(yùn)算進(jìn)行諧波分析；通用異步收發(fā)器等技術(shù)。 - It's difficult to find asynchronous receiver in a sentence. 用asynchronous receiver造句挺難的
- In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future
第五章提出了基于ieee754浮點(diǎn)標(biāo)準(zhǔn)的浮點(diǎn)運(yùn)算處理器的設(shè)計(jì)和異步串行通信核的設(shè)一浙江大學(xué)博士學(xué)位論文計(jì)，提出了適合硬件實(shí)現(xiàn)的浮點(diǎn)乘除法、加減運(yùn)算的結(jié)構(gòu)，浮點(diǎn)運(yùn)算處理器主要用于高速fft浮點(diǎn)處理功能，異步串行通信核主要用于pft處理器ip核的外圍擴(kuò)展模塊以及本文所做的驗(yàn)證測(cè)試平臺(tái)中的數(shù)據(jù)接口部分第六章提出了面向系統(tǒng)級(jí)芯片的可測(cè)試性設(shè)計(jì)包括了基于掃描測(cè)試atpg 、內(nèi)建自測(cè)試bist 、邊界掃描測(cè)試jtag設(shè)計(jì)，在討論可測(cè)試性設(shè)計(jì)策略選擇的問題上，提出了針對(duì)不同模塊進(jìn)行的分別測(cè)試策略，提出了層次化jtag測(cè)試方法和掃描總線法，提出了基于fpga